1. Field of the Invention
The present invention relates to a method for creating an impedance controlled printed wiring board. More particularly, the invention is directed to the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, the invention is also directed to the provision of a method for producing an impedance controlled printed circuit wiring board. Moreover, the invention is further directed to the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.
In essence, problems are encountered in the technology with regard to the production of printed wiring boards and which incorporate so-called deep blind vias while maintaining tight and stringent impedance control.
Presently, printed-wiring board (PWB) products which are intended for high frequency applications are provided with plated through holes (PTH's) extending through the thickness of the board thickness, and resultingly creating an antenna which can adversely affect signal integrity. Thus, by terminating the plated through holes at specific layers within the printed wiring board, the undesired antenna effect is substantially reduced or possibly even completely eliminated.
Basically, high frequency printed wiring boards necessitate an extremely tight control over impedance, such as along differential depths, board edges and alike, in order to maintain high levels of signal integrity. Consequently, in the construction of multi-layer printed wiring boards, the copper plating thicknesses which are provided on the various board innerlayers as well as the innerlayer spacings must be tightly and precisely controlled. However, inasmuch as the innerlayers are actually substructures containing plated through holes (PTH's) the surface copper thickness on the substructures may quite possibly exceed the thickness required for impedance control; in effect, the thickness comprised of the base foil plus the plated copper. This necessitates that the copper surface must be thinned down without etching the plating in the holes.
2. Discussion of the Prior Art
Although various types of multilayer and single-layer structures for printed wiring boards (PWB) and printed circuit boards (PCB) have been developed in the technology, none of these address themselves directly to solving the problem associated with the providing of tightly controlled impedances through structures and methods which will facilitate attainment of satisfactory levels of signal integrity.
Bhatt et al. U.S. Pat. No. 5,822,856 describes a process for the hole filling of a plated through hole (PTH) for a single-layer circuit board. There is no discussion of any copper thinning, varying copper thicknesses or providing for impedance control in order to eliminate problem which are encountered with regard to adverse effects on signal integrity.
Kahlert et al. U.S. Pat. No. 5,336,855 relates to a multilayer printed circuit board which is employed for high-frequency operation and wherein the characteristic impedance is controlled through the creation of isolated metal islands which are connected to ground. The metallization layers in the structure of this patent are of equal thickness and there is no disclosure of varying copper thicknesses on different board layers and wherein there is no plated through hole fill material provided in the structure.
Swift et al. U.S. Pat. No. 5,281,771 pertains to a multilayer wiring board with interlevel connectors, and to a method for producing the structure which provides for carbon fibers in order to form electrical interconnects between the layers. There is no discussion nor suggestion of utilizing the thinning of copper deposits on innerlayers of printed wiring board in order to provide for impedance control allowing for improved levels of signal integrity.
Strobel U.S. Pat. Nos. 4,661,654 and 4,610,756 each disclose printed circuit boards and manufacturing processes which do not direct themselves to reduction of plated copper layers or using a plated hole fill other than a hole filled with solder for pin insertion. Consequently, there is no suggestion nor disclosure of providing an impedance control so to resultingly improve signal integrity in a manner analogous with that disclosed by the present invention.
Tanaka et al, U.S. Pat. No. 3,673,680 discloses a method of fabricating printed wiring boards wherein a relatively heavy solder layer is provided at locations at which electrical and mechanical connections are required. There is no discussion nor disclosure of any multilayer substrate or of reducing the thickness of plated copper layers and of using a plated through hole fill other than having a hole filled with a solder to facilitate pin insertion.
As described in the publication “Innovations in Base Materials and Polymer Applications”, European Institute of Printed Circuits, 1994, this article merely discloses the impact on process yields of using a positive working ED resist so as to provide improved conductive contrast, resolution and conductive geometry in the construction of printed circuit boards. There is no discussion of any reducing copper layer thicknesses in a manner so as to control impedance of printed wiring boards which would effect signal integrity.
Finally, the article “High Density MLB's With New Materials and Build-up Technologies”, Printed Circuit World Convention VII Proceedings of May 1996 describe the utilization of new materials and the forming of multilayer laminates so as to provide improved innerlayer structures and buried via holes or blind via holes to resultingly improve higher density as well as higher accuracy in the electronic equipment and to also provide an environmentally-friendly enhanced printed circuit boards. There is no disclosure of utilizing the inventive aspect of thinning copper layers in a multilayer printed wiring board structure with the aspect of multiple differential impedance control layers.